Digital Systems: From Logic Gates to Processors Week 7 Quiz Answer

Digital Systems: From Logic Gates to Processors Week 7 Quiz Answer

In this article i am gone to share Coursera Course: Digital Systems: From Logic Gates to Processors Week 7 Quiz Answer with you..

Graded Quiz 7 Answer

Question 1)

VHDL processes of Figure 1 describe the operation of a movement-direction detector similar to that studied in lecture L7.3. It is assumed that we have previously defined the inputs "x" (2-bit signal whose components are x(1), x(0)), "clk" and "reset"; the output "z" and the signals "cs" and "nextState", which can take the values (0,1,2,3).

We want to design a sequential circuit that implements this motion detector, and to do so we have thought in using a block design as the one shown in Figure 2: The second block contains a 2-bit register storing the internal state of the circuit (nextState), and the first block contains a combinational circuit responsible for calculating (1) the next state (nextState) from the current state (cs) and the inputs (x), and (2) the output "z", also from the current state and inputs.

Mark which of the following circuit implements the "COMBINATIONAL CIRCUIT" module of Figure 1.

Note: In the circuits shown as solutions, the "x2" symbol framed in a square or circle means that the input or output signal has 2 bits. The "x1" symbol means that the signal has 1 bit.

Figure 1: VHDL code.

synchronization: process (reset, clk)

begin

if reset = '1' then cs <= 0;

elsif clk'event and clk = '1' then cs<=nextState;

end if;

end process synchronization;

mov_det: process (cs, x)

begin

nextState <= cs;

case cs is

when 0 => z <= x(1);

case X is

when 1 => nextState := 1;

when 3 => nextState := 3;

end case;

when 1 => z <= not(x(0);

case X is

when 2 => nextState := 0;

when 3 => nextState := 2;

end case;

when 2 => z <= not(x(1));

case X is

when 0 => nextState := 1;

when 2 => nextState := 3;

end case;

when 3 => z <= x(0);

case X is

when 0 => nextState := 0;

when 1 => nextState := 2;

end case;

end process mov_det;

Answer:

Question 2)

Given an n-bit natural X and an integer E represented under the form (-1)SIGN.|E|, the shifting algorithm shown in figure 1 computes an n-bit natural M such that

When E ≥ 0, E trailing zeroes are added and E leading bits are removed.

When E < 0, |E| leading zeroes are added and |E| trailing bits are removed.

Example (n = 14):

If X = 01110111010010 and E = 5 then M=11101001000000;

If X = 01110111010010 and E = -5 then M=00000011101110;

Figure 2 shows a sequential machine that implements this algorithm for n=4 and |E|=3, where:

M and next_M are 4-bits numbers; count and next_count are 2-bits numbers and done and next_done are 1-bit numbers.

The bits of M, next_M, count and next_count are named as follows: M = {M3, M2,M1,M0}>; next_M = {next_M3,next_M2,next_M1,next_M0}; count={count1,count0}; next_count={next_count1,next_count0}

When reset=1, count, M and done are respectively set to |E|, X and 0. What are the Boolean functions for next_count and next_done?

M <= X; done <= 0; count <= |E|;

loop

if (count > 0) and (done = 0) then

if SIGN=0 then M<=M(n-2 downto 0)&0; -- (Note1)

else M<=0&M(n-1 downto 1); -- (Note2)

end if;

else done <= 1;

end if;

if done=0 then count <= count - 1; end if;

end loop;

----------

-- Note1: This sentence computes M<=M•2 by shifting the bits of

-- M one position left and setting M(0)=0.

-- Note2: This sentence computes M<=M/2 by shifting the bits of

-- M one position right and setting M(n-1)=0.

----------

Answer:

Question 3)

EXERCISE 7.3.a: The VHDL codes associated with every answer can be found in file quiz7.pdf included in "Reading : QUIZ 7 INSTRUCTIONS".

A stack (figure1) is a memory that works as follows:

if a write_request is received, then data_in is "pushed into" the stack;

if a read_request is received, then data_out> is "pulled out" of the stack.

We want to model the stack in VHDL by using a single "process". For that we use :

An array stored_data that represents the data stored within the stack. Stored_data has n components: {stored_data(0),stored_data(1), … , stored_data(n-1)}

A natural variable address that points to the component of array stored_data where the next data should be stored,

A binary variable (flag) empty, equal to "true" if all data have been pulled out of the stack, and

A binary variable (flag) full equal to "true" if all n stack positions are occupied.

Assume that a write operation will never be requested when the stack is full and a read operation will never be requested when the stack is empty. Assume also that there are never simultaneous read and write requests.

Select the VHDL code that describes this stack.

Note: conv_integer(x) converts x to an integer. Zero and one are previously defined constants equal to 0 and 1 respectively. Max_address is the size of the stack (max_address=n)

CODE 2

CODE 1

CODE 3

CODE 4

Question 3)

EXERCISE 7.3.b: The VHDL codes associated with every answer can be found in file quiz7.pdf included in "Reading : QUIZ 7 INSTRUCTIONS".

A queue (figure1) is a memory that works as follows:

if a write_request is received, then data_in is "pushed into" the queue;

if a read_request is received, then data_out is "pulled out" of the queue.

We want to model the queue in VHDL by using a single "process". For that we use:

An array stored_data that represent the data stored within the queue; it has n components {stored_data(0),stored_data(1), ... , stored_data(n-1)};

A natural variable write_address that points to the component of array stored_data where the next data should be stored,

A natural variable read_address that points to the component of array stored_data that should be pulled out,

A natural number, named number, equal to the number of data in the queueA binary variable (flag) empty>, equal to "true" if all data have been pulled out of the queue, and

A binary variable (flag) full, equal to "true" if all n queue positions are occupied.

Assume that a write operation will never be requested when the queue is full and a read operation will never be requested when the queue is empty. Assume also that there are never simultaneous read and write requests.

Select the VHDL code that describes this queue.

Note: conv_integer(x) converts x to an integer. Zero and one are previously defined constants equal to 0 and 1 respectively. Max_number_minus_1 is the size of the queue minus 1 (max_number_minus_1=n-1).

CODE 5

CODE 6

~~CODE 7~~

CODE 8

Question 4)

EXERCISE 7.4.b: The VHDL codes associated with every answer can be found in file quiz7.pdf included in "Reading : QUIZ 7 INSTRUCTIONS".

A queue (figure1) is a memory that works as follows:

if a write_request is received, then data_in is "pushed into" the queue;

if a read_request is received, then data_out is "pulled out" of the queue.

We want to model the queue in VHDL by using two processes The first one is a Moore finite state machine that controls the sequence of operations and where its output state is equal to its internal state. The second defines the operations. For that we use:

An array stored_data that represent the data stored within the queue; it has n components {stored_data(0),stored_data(1), ... , stored_data(n-1)}

A natural variable write_address that points to the component of array stored_data where the next data should be stored,

A natural variable read_address that points to the component of array stored_data that should be pulled out,

A natural number, named number, equal to the number of data in the queue

A binary variable (flag) empty, equal to "true" if all data have been pulled out of the queue, and

A binary variable (flag) full, equal to "true" if all n queue positions are occupied.

Select the VHDL code that describes this queue.

~~CODE 13~~

CODE 14

~~CODE 15~~

CODE 16

Question 4)

EXERCISE 7.4.a: The VHDL codes associated with every answer can be found in file quiz7.pdf included in "Reading : QUIZ 7 INSTRUCTIONS".

A stack (figure1) is a memory that works as follows:

if a write_request is received, then data_in is "pushed into" the stack;

if a read_request is received, then data_out is "pulled out" of the stack.

We want to model the stack in VHDL by using two processes. The first one describes a Moore finite state machine that controls the sequence of operations, and where its output state is equal to its internal state. The second defines the operations. For that we use :

An array stored_data that represents the data stored within the stack. Stored_data has n components: {stored_data(0),stored_data(1), … , stored_data(n-1)}

A natural variable address that points to the component of array stored_data where the next data should be stored,

A binary variable (flag) empty, equal to "true" if all data have been pulled out of the stack, and

A binary variable (flag) full, equal to "true" if all n stack positions are occupied.

Select the VHDL code that describes this stack.

Note: conv_integer(x) converts x to an integer. Zero and oneare previously defined constants equal to 0 and 1 respectively. Max_address is the size of the stack (max_address=n)

CODE 9

CODE 10

CODE 11

CODE 12

Question 5)

EXERCISE 7.5: The VHDL codes associated with every answer can be found in file quiz7.pdf included in "Reading : QUIZ 7 INSTRUCTIONS".

We want to define a finite state machine (FSM) that controls the execution of a two-branch process (figure 1):

On a positive edge of start, if branch_selection = 0 then the control signal branch_1 goes high and the processor starts executing the first branch;

If branch_selection = 1 then the control signal branch_2 goes high and the processor starts executing the second branch.

When the processor completes its task (first or second branch), it raises the signal (flag) done.

Then, the control signal branch_1 or branch_2 (the one that has been raised) goes low, the processor lowers done, and the control circuit waits for another positive edge on start.

Select the VHDL code that models the FSM “control”.