Digital Systems: From Logic Gates to Processors Week 5 Quiz Answer

Digital Systems: From Logic Gates to Processors Week 5 Quiz Answer

In this article i am gone to share Coursera Course: Digital Systems: From Logic Gates to Processors Week 5 Quiz Answer with you..

Graded Quiz 5 Answer

Question 1)

Which statement is true?

The frequency of a clock signal with period T=20ns is 50KHz.

The memory elements with asynchronous inputs (reset and/or set) can change their state only when these signals are active.

The duration of the positive pulse and the negative pulse of the clock signal may be different.

The clock signal controls that the outputs of all the logic gates of the circuit change their value at the same time.

Question 2)

Complete the following time chart

Instructions to answer this question

1) In the virtual machine, open VerilUOC_Desktop, click on Simulate-> Verification and then click on the VerilChart tab.

2) In "Module" select "Graded Exercises", click on exercise 5.2.a and enter the time chart.

3) Click on Verify (bottom-right corner). VerilChart returns a 4 uppercase letters code. Type it in the answer box.

GXTC
RZCY
KBAH

Question 3)

The graph shown in figure 1 describes a 3-input (x2, x1, x0), 2-output (Z1, Z0) sequential circuit. Assume that the initial state is “A” and write the sequence of states and outputs reached by the circuit when the input pattern shown in table 1 is received.

Note: Write the state/output pairs at t0, t1, t2 and t3, separated by a space. Example: If in t0 the circuit goes from A to C and output associated to state C is 11, then in t1 remains at C; in t2 changes to state D with an output associated to state D equal to 00, and finally in t3 changes to state E with output 10, you should write C/11 C/11 D/00 E/10

Answer: D/0 C/0 A/1 A/0

Question 4)

We want to design a circuit that controls the opening and closing of an access gate for vehicles. The control system receives 4 input signals:

Request: Comes from a button that the vehicle’ driver presses (Request=1) to open the gate.

Upper: Comes from a sensor in the gate. Takes value 1 when the gate is fully open.

Lower: Comes from a sensor in the gate. Takes value 1 when the gate is fully closed.

Sensors: Comes from sensors located in the "gate area" (see figure). Takes value 0 when that area is free of vehicles.

The control circuit generates 2 outputs:

ON/OFF: Motor power off (ON/OFF=0) or power on (ON/OFF=1)

UP/DOWN: Indicates the direction of the gate movement.

Open the gate: ON/OFF=1, UP/DOWN=0

Close the gate: ON/OFF=1, UP/DOWN=1

The control circuit must perform the following sequence of operations:

Wait for an access request signal (Request=1)

Open the gate (ON/OFF=1, UP/DOWN=0)

Wait until the gate is fully open (Upper=1)

Wait until the gate area is clear of vehicles (Sensors=0) and begin to close the door (ON/OFF=1, UP/DOWN=1)

Wait until the gate fully closed (Lower=1) and return to the initial state, waiting for a new “Request” signal. .

No new access request will be attended until this sequence of events is completed.

Which of the following graphs defines the circuit?

(Note: Let’s see that only one signal appears on every edge. That means that the transition to the new state depends only on this signal, independently of the values of the rest of the signals)

Answer:

Question 5)

Assuming that states S0, S1 and S2 have been codified as S0: 00; S1: 10; y S2: 11, complete the following state transition table and the output table of figure 1.

Be carefull with the states' codes

Note: Write the table entering the "Next state" column from top to bottom, separating the states with a white space, and then the "Output" column, in the same order, with a white space between outputs. Example: Table of figure 2 should be entered as 11 11 00 00 xx xx 00 01 1 0 1 0 x x 1 0 ("x" lowercase)

Answer: 01 00 11 00 xx xx 11 00 0 1 0 0 x x 0 1

Question 6)

Design and draw a sequential circuit having one input X and one output Y that implements the behavior shown in table 1.Name inputs and outputs of the circuit as shown in figure1 (X, RST, clk, Y).State S0 should be coded as 00.

Very important note: The VerilUOC_Desktop verifier requires that all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "wiring", select "Constant" and connect the constant (a logical 1) to the “load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.